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SY898530U
500MHz 1:16 3.3V-to-2.5V LVPECL Fanout Buffer
General Description
The SY898530U is a 1:16 Fanout buffer which can accept most standard differential logic levels and outputs the signal as a differential 2.5V LVPECL signal. The part can amplify input signals as small as 150mVpp to the full LVPECL output swing. The SY898530U is well suited for clock distribution applications which demand versatility and low-skew performance. It is pin-to-pin compatible with IDT's ICS8530 fanout buffer. The SY898530U operates from a 3.3V 5% core power supply and a 2.5V 5% output supply and is guaranteed over the full commercial temperature range (0C to +70C). It is available in a 48-pin TQFP lead-free package. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
Features
* 16 Differential 2.5V LVPECL outputs * Differential CLK inputs. Accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL logic levels * Translates any single-ended input signal to 2.5V LVPECL levels with a resistor bias on /CLK input * 500MHz maximum output frequency * <50ps output skew * <250ps part-to-part skew * <2ns propagation delay * 3.3V Core, 2.5V output operating supply * 0C to +70C operating temperature * Available in 48-pin TQFP package * Pin-to-pin compatible with ICS8530
Functional Block Diagram
Applications
* * * * Data distribution High-performance PCs Communications Parallel processor-based systems
Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
January 2011
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SY898530U
Ordering Information
Part Number SY898530UTZ SY898530UTZTR SY898530UTZTX
Notes: 1. 2. 3. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. Tape and Reel. EIA specification orientation.
(2) (2, 3)
Package Type TQFP-48 TQFP-48 TQFP-48
Operating Range Commercial Commercial Commercial
Package Marking SY898530UTZ with Pb-Free bar-line indicator SY898530UTZ with Pb-Free bar-line indicator SY898530UTZ with Pb-Free bar-line indicator
Lead Finish Matte-Sn Matte-Sn Matte-Sn
Pin Configuration
48-Pin TQFP (TQFP-48)
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SY898530U
Pin Description
Pin Number 36, 37 33, 34 31, 32 28, 29 26, 27 22, 23 20, 21 17, 18 15, 16 9, 10 7, 8 4, 5 2, 3 46, 47 44, 45 41, 42 39, 40 1, 11, 14, 24, 25, 35, 38, 48 12, 13 6, 19, 30, 43 Pin Name CLK, /CLK Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 Q10, /Q10 Q11, /Q11 Q12, /Q12 Q13, /Q13 Q14, /Q14 Q15, /Q15 VCCO VCC VEE Output Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCCO pins as possible. Supplies the output buffers. Core Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. Supplies input and core circuitry. Ground 2.5V LVPECL Differential Output Pairs. Differential buffered copies of the input signal. The output swing is typically 740mV. See Interface Applications for termination information. Pin Function Differential Clock Inputs. Accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL logic levels. CLK is internally connected to a pull-down resistor, /CLK is internally connected to a pullup resistor. See "Pin Characteristics" for typical values.
Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Description Input Capacitance Input Pull Up Resistor Input Pull Down Resistor Min. Typ. 4 50 30 Max. Units pF K K
Clock Input Function Table
Inputs CLK 0 1 0 1 Biased
Note: 1. Refer to Interface Applications for Single-Ended Interfaces.
(1)
Outputs /CLK 1 0 Biased(1) Biased 0 1
(1)
Qx Low High Low High High Low
/Qx High Low High Low Low High
Input to Output Mode Differential to Differential Differential to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential
Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting
Biased(1)
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SY898530U
Absolute Maximum Ratings(1)
Supply Voltage (VCC)................................................4.6V Input Voltage (VIN) ............................-0.5V to VCC + 0.5V LVPECL Output Current (IOUT) Continuous.......................................................50mA Surge .............................................................100mA Lead Temperature (soldering, 20sec.).................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ......................... 3.135V to 3.465V Output Supply Voltage (VCCO)............ 2.375V to 2.625V Ambient Temperature (TA)........................0C to +70C Package Thermal Resistance(3) TQFP Still-air (JA) .........................................48C/W Junction-to-Case (JC).........................25C/W
DC Electrical Characteristics(6)
VCC = 3.135V to 3.465V, VCCO = 2.375V to 2.625V, TA = 0C to +70C, unless otherwise stated. Symbol VCC VCCO IEE IIH IIL VPP VCMR Parameter Power Supply Voltage Range Output Power Supply Power Supply Current Input HIGH Current Input LOW Current CLK /CLK CLK /CLK Max. VCC, VCCO VCC = VIN = 3.465V VCC = 3.465V, VIN = 0.5V -5 -150 0.15 Note 4, 5 0.5 1.3 Vcc - 0.85 Condition Min. 3.135 2.375 Typ. 3.3 2.5 Max. 3.465 2.625 125 150 5 mA uA uA uA uA V V Units V
Peak-to-Peak Input Swing Common Mode Input Voltage
PECL Outputs DC Electrical Characteristics(6)
VCC = 3.135V to 3.465V, VCCO = 2.375V to 2.625V, TA = 0C to +70C, Outputs terminated with 50 to VCCO-2V unless otherwise stated. Symbol VOH VOL VOUT
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 4. For single-ended applications, the maximum input voltage for CLK, /CLK is VCC+0.3V. 5. Common mode voltage is defined as VIH. 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing
Condition
Min. VCCO - 1.1 VCCO - 2.0 0.55
Typ.
Max. VCCO - 0.7 VCCO - 1.4 0.93
Units V V V
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SY898530U
AC Electrical Characteristics
VCC = 3.135V to 3.465V, VCCO = 2.375V to 2.625V, TA = 0C to +70C, unless otherwise stated. Symbol fMAX tPD tSkew tJITTER tR, tF Parameter Maximum Frequency Propagation Delay Output-to-Output skew Part-to-Part Skew Integration Range = 12kHz - 20MHz Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 7. 8. 9. Measured from the differential input crossing point to the differential output crossing point. Output-to-Output skew is the difference in time between outputs, receiving data from the same input, for the same temperature, voltage and transition. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
Condition Note 7 Note 8, 10 Notes 9, 10 Output = 312MHz At full output swing.
Min. 500 1
Typ.
Max. 2
Units MHz ns ps ps fs
26 477 300 47 50
50 250
700 53
ps %
10. This parameter is defined in accordance with JEDEC Standard 65.
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SY898530U
Phase Noise Graph
Phase Noise Plot: 312MHz @ 3.3V
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SY898530U
Test Circuit
Differential Input Level
Output Duty Cycle
Propagation Delay
Output Rise/Fall Times
Output-to-Output Skew
Part-to-Part Skew
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Typical Characteristics
VCC = 3.3V, VCCO = 2.5V, TA = 25C, Input Signal = 800mV
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Output Interface Applications
Figure 1. Parallel Termination-Thevenin Equivalent
Notes: 1. For +2.5V systems: R1 = 250, R2 = 82.5. 2. For +5.0V systems: R1 = 82, R2 = 130.
Figure 2. Three-Resistor "Y-Termination"
Notes: 1. Power-saving alternatives to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46 to 50. For +5V systems, Rb = 110.
Figure 3. Terminating Unused I/O
Notes: 1. Unused output (/Q) must be terminated to balance the output. 2. For 2.5V systems: R1 = 250, R2 = 62.5, R3 = 1.25k, R4 = 1.2k.
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SY898530U
Input Interface Applications
Figure 4. CLK and /CLK Input Driven By 1.8V LVHSTL
Figure 5. CLK and /CLK Input Driven By 3.3V LVDS Driver
Figure 6. CLK and /CLK Input Driven By 3.3V LVPECL Driver with AC Couple
Notes: 1. For +2.5V systems: R1 & R2 = 250, R3 & R4 = 82.5. 2. For +5.0V systems: R1 & R2 = 82, R3 & R4 = 130.
January 2011
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SY898530U
Package Information
48-Pin TQFP (TQFP-48)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2009 Micrel, Incorporated.
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